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RISC-V_Verilog
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Fix: readme checkbox 2

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brice.boisson 2023-10-25 09:02:19 +09:00
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README.md
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@ -3,7 +3,7 @@
This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose. This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.
This CPU will implement the RV32I ISA, with the following goal: This CPU will implement the RV32I ISA, with the following goal:
- [] Single cycle RISC-V RVI32I CPU - [ ] Single cycle RISC-V RVI32I CPU
- [] Multi cycle CPU - [ ] Multi cycle CPU
- [] Pipelining - [ ] Pipelining
- [] (Bonus) RISC-V privileged ISA - [ ] (Bonus) RISC-V privileged ISA