brice/RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix: dynamique test bench else cond

Browse Source
This commit is contained in:
brice.boisson
2023-11-26 22:22:16 +09:00
parent 9d82414a58
commit c6ffe7e2e9
1 changed files with 2 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
tb/tb_risc_v_cpu-dyn.v
View File

@@ -98,7 +98,6 @@ module tb_risc_v_cpu ();
test[instruction_addr][5:0] = reg_number; test[instruction_addr][5:0] = reg_number;
test[instruction_addr][37:6] = reg_test_value; test[instruction_addr][37:6] = reg_test_value;
end else if (test[instruction_addr][43:38] == 6'b111111) begin end else if (test[instruction_addr][43:38] == 6'b111111) begin
$display ("1");
test[instruction_addr][43:38] = reg_number; test[instruction_addr][43:38] = reg_number;
test[instruction_addr][75:44] = reg_test_value; test[instruction_addr][75:44] = reg_test_value;
end else if (test[instruction_addr][81:76] == 6'b111111) begin end else if (test[instruction_addr][81:76] == 6'b111111) begin
@@ -142,10 +141,10 @@ module tb_risc_v_cpu ();
`assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]]) `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]])
end end
end end
end end else begin
else
`next_cycle `next_cycle
end end
end
/* Test State After Execution */ /* Test State After Execution */
code_file_inputs = $fopen("./final_test.tmp", "r"); code_file_inputs = $fopen("./final_test.tmp", "r");