brice/RISC-V_Verilog
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Add: begining bubble sort test | Fix: branch and imm value extension

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brice.boisson
2023-10-25 11:07:19 +09:00
parent a15dc204e5
commit db5d909402
6 changed files with 105 additions and 8 deletions
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10
rtl/decoder.v
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@@ -93,7 +93,7 @@ endfunction
end
OP_IMM : begin // OP-IMM - Addi, ...
imm[11:0] = instruction[31:20];
imm[31:12] = (instruction[14:12] == 3'b011 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[14:12] == 3'b011 || instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 1;
reg_sel_data_in = 2'b00;
reg_sel_out_a = instruction[19:15];
@@ -108,7 +108,7 @@ endfunction
end
LOAD : begin // LOAD - Lw, ...
imm[11:0] = instruction[31:20];
imm[31:12] = (instruction[14:12] == 3'b100 || instruction[14:12] == 3'b101 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[14:12] == 3'b100 || instruction[14:12] == 3'b101 || instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 1;
reg_sel_data_in = 2'b01;
reg_sel_out_a = instruction[19:15];
@@ -123,7 +123,7 @@ endfunction
end
STORE : begin // STORE - Sw, ...
imm[11:0] = {instruction[31:25], instruction[11:7]};
imm[31:12] = (instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 0;
reg_sel_data_in = 2'b00;
reg_sel_out_a = instruction[19:15];
@@ -138,7 +138,7 @@ endfunction
end
BRANCH : begin // BRANCH - Beq, ...
imm[11:0] = {instruction[31:25], instruction[11:7]};
imm[31:12] = (instruction[14:12] == 3'b110 || instruction[14:12] == 3'b111 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[14:12] == 3'b110 || instruction[14:12] == 3'b111 || instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 0;
reg_sel_data_in = 2'b00;
reg_sel_out_a = instruction[19:15];
@@ -168,7 +168,7 @@ endfunction
end
JALR : begin // JUMP REG - Jalr
imm[11:0] = instruction[31:20];
imm[31:12] = (instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 1;
reg_sel_data_in = 2'b10;
reg_sel_out_a = instruction[19:15];

2
rtl/instruction.v
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@@ -1,7 +1,7 @@
module instruction (input [31:0] address,
output [31:0] instruction);
reg [7:0] memory [63:0];
reg [7:0] memory [127:0];
assign instruction = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};

2
rtl/memory.v
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@@ -4,7 +4,7 @@ module memory (input clock, reset,
input [31:0] data_in,
output [31:0] data_out);
reg [7:0] memory [63:0];
reg [7:0] memory [127:0];
always @(posedge clock, posedge reset) begin
if (reset == 1)

2
rtl/risc_v_cpu.v
View File

@@ -65,7 +65,7 @@ module risc_v_cpu (input clock, reset,
mux2_1 #(2) mux2_pc_sel_branch (
.in_1(pc_is_branch),
.in_2({alu_out[1], (alu_not ? ~alu_out[0] : alu_out[0])}),
.in_2({0, (alu_not ? (~alu_out != 32'b0 ? 1 : 0) : (alu_out != 0 ? 1 : 0))}),
.sel(pc_is_jmp),
.out(pc_sel_in)
);