brice
/
RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add: begining bubble sort test | Fix: branch and imm value extension

This commit is contained in:
brice.boisson 2023-10-25 11:07:19 +09:00
parent a15dc204e5
commit db5d909402
6 changed files with 105 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -0,0 +1 @@
.vscode

10
rtl/decoder.v
View File

@ -93,7 +93,7 @@ endfunction
end
OP_IMM : begin // OP-IMM - Addi, ...
imm[11:0] = instruction[31:20];
imm[31:12] = (instruction[14:12] == 3'b011 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[14:12] == 3'b011 || instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 1;
reg_sel_data_in = 2'b00;
reg_sel_out_a = instruction[19:15];
@ -108,7 +108,7 @@ endfunction
end
LOAD : begin // LOAD - Lw, ...
imm[11:0] = instruction[31:20];
imm[31:12] = (instruction[14:12] == 3'b100 || instruction[14:12] == 3'b101 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[14:12] == 3'b100 || instruction[14:12] == 3'b101 || instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 1;
reg_sel_data_in = 2'b01;
reg_sel_out_a = instruction[19:15];
@ -123,7 +123,7 @@ endfunction
end
STORE : begin // STORE - Sw, ...
imm[11:0] = {instruction[31:25], instruction[11:7]};
imm[31:12] = (instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 0;
reg_sel_data_in = 2'b00;
reg_sel_out_a = instruction[19:15];
@ -138,7 +138,7 @@ endfunction
end
BRANCH : begin // BRANCH - Beq, ...
imm[11:0] = {instruction[31:25], instruction[11:7]};
imm[31:12] = (instruction[14:12] == 3'b110 || instruction[14:12] == 3'b111 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[14:12] == 3'b110 || instruction[14:12] == 3'b111 || instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 0;
reg_sel_data_in = 2'b00;
reg_sel_out_a = instruction[19:15];
@ -168,7 +168,7 @@ endfunction
end
JALR : begin // JUMP REG - Jalr
imm[11:0] = instruction[31:20];
imm[31:12] = (instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
imm[31:12] = (instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
reg_we = 1;
reg_sel_data_in = 2'b10;
reg_sel_out_a = instruction[19:15];

2
rtl/instruction.v
View File

@ -1,7 +1,7 @@
module instruction (input [31:0] address,
output [31:0] instruction);
reg [7:0] memory [63:0];
reg [7:0] memory [127:0];
assign instruction = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};

2
rtl/memory.v
View File

@ -4,7 +4,7 @@ module memory (input clock, reset,
input [31:0] data_in,
output [31:0] data_out);
reg [7:0] memory [63:0];
reg [7:0] memory [127:0];
always @(posedge clock, posedge reset) begin
if (reset == 1)

2
rtl/risc_v_cpu.v
View File

@ -65,7 +65,7 @@ module risc_v_cpu (input clock, reset,
mux2_1 #(2) mux2_pc_sel_branch (
.in_1(pc_is_branch),
.in_2({alu_out[1], (alu_not ? ~alu_out[0] : alu_out[0])}),
.in_2({0, (alu_not ? (~alu_out != 32'b0 ? 1 : 0) : (alu_out != 0 ? 1 : 0))}),
.sel(pc_is_jmp),
.out(pc_sel_in)
);

96
tb/tb_risc_v_cpu.v
View File

@ -178,6 +178,102 @@ module tb_risc_v_cpu ();
`assert_no_wait("FIBO VALUE 12: 144", risc_v_cpu.registers_bank.registers[7], 144)
`assert_no_wait("FIBO CYCLE 12: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
/* Reset */
reset = 1'b1;
#10
reset = 1'b0;
clk = 1'b0;
/* BUBBLE SORT
int len = 10;
int array[] = {10, 9, 8, 7, 6, 5, 4, 3, 2, 1};
for (int i = len - 1; i > 0; i--)
{
for (int j = 0; j < i; j++)
{
if (array[j] > array[j + 1])
{
int temp = array[j];
array[j] = array[j + 1];
array[j + 1] = temp;
}
}
}
*/
/* BUBBLE SORT */
/* ADDi $10, R[0], R[1] - R[1] = 10 */
/* "000000001010_00000_000_00001_0010000" */
risc_v_cpu.uut_instruction.memory[0] = 8'b10010000;
risc_v_cpu.uut_instruction.memory[1] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[2] = 8'b10100000;
risc_v_cpu.uut_instruction.memory[3] = 8'b00000000;
/* ADDi $10, R[0], R[2] - R[2] = 10 */
/* "000000001010_00000_000_00010_0010000" */
risc_v_cpu.uut_instruction.memory[4] = 8'b00010000;
risc_v_cpu.uut_instruction.memory[5] = 8'b00000001;
risc_v_cpu.uut_instruction.memory[6] = 8'b10100000;
risc_v_cpu.uut_instruction.memory[7] = 8'b00000000;
/* ADDi $0, R[0], R[3] - R[2] = 10 */
/* "000000000000_00000_000_00011_0010000" */
risc_v_cpu.uut_instruction.memory[8] = 8'b10010000;
risc_v_cpu.uut_instruction.memory[9] = 8'b00000001;
risc_v_cpu.uut_instruction.memory[10] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[11] = 8'b00000000;
/* STR $0, R[0], R[2], MEM[0] = 10 */
/* "0000000_00010_00000_000_00000_0100000" */
risc_v_cpu.uut_instruction.memory[12] = 8'b00100000;
risc_v_cpu.uut_instruction.memory[13] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[14] = 8'b00100000;
risc_v_cpu.uut_instruction.memory[15] = 8'b00000000;
/* ADDi $-1, R[2], R[2] - R[2] = 9 */
/* "111111111111_00010_000_00010_0010000" */
risc_v_cpu.uut_instruction.memory[16] = 8'b00010000;
risc_v_cpu.uut_instruction.memory[17] = 8'b00000001;
risc_v_cpu.uut_instruction.memory[18] = 8'b11110001;
risc_v_cpu.uut_instruction.memory[19] = 8'b11111111;
/* ADDi $1, R[3], R[3] - R[3] = 1 */
/* "000000000001_00011_000_00011_0010000" */
risc_v_cpu.uut_instruction.memory[20] = 8'b10010000;
risc_v_cpu.uut_instruction.memory[21] = 8'b10000001;
risc_v_cpu.uut_instruction.memory[22] = 8'b00010001;
risc_v_cpu.uut_instruction.memory[23] = 8'b00000000;
/* BNE -8, R[0], R[2] - R[2] = 9 */
/* "1111111_00010_00000_001_10111_1100000" */
risc_v_cpu.uut_instruction.memory[24] = 8'b01100000;
risc_v_cpu.uut_instruction.memory[25] = 8'b00011100;
risc_v_cpu.uut_instruction.memory[26] = 8'b00100000;
risc_v_cpu.uut_instruction.memory[27] = 8'b11111110;
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`end_message
end