brice/RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add: generate file on make

Browse Source
This commit is contained in:
brice.boisson
2023-11-21 18:45:25 +09:00
parent 7d60960831
commit e2ca11548c
5 changed files with 12 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
tb/tb_risc_v_cpu-dyn.v
View File

@@ -53,7 +53,6 @@ module tb_risc_v_cpu ();
read_instruction_2 = $fgetc(bin_file_inputs);
read_instruction_3 = $fgetc(bin_file_inputs);
read_instruction_4 = $fgetc(bin_file_inputs);
$display("read_instruction_1: %b", read_instruction_1);
if (
read_instruction_1[8] != 1'b1 &&
@@ -91,8 +90,6 @@ module tb_risc_v_cpu ();
$finish;
end
$display ("Line %d: %d:%b=%b ]", res, instruction_addr, reg_number, reg_test_value);
if (test[instruction_addr][5:0] == 6'b111111) begin
test[instruction_addr][5:0] = reg_number;
test[instruction_addr][37:6] = reg_test_value;
@@ -156,7 +153,6 @@ module tb_risc_v_cpu ();
while (!$feof(code_file_inputs))
begin
res = $fscanf(code_file_inputs, "%d=%d\n", reg_number, reg_test_value);
$display ("Line %d: %b=%b ]", res, reg_number, reg_test_value);
if (res != 2) begin // If fscanf failed, the test file structure is wrong, then exit
$display("Parsing test file failed");
$finish;

5
tb/test_source_code/tb_riscv_cpu/test.S
View File

@@ -1,11 +1,10 @@
# t0 = 0
li t0, 0
li t2, 10 # R[2]=10, MEM[1]=6
li t0, 0 # R[5]=0
li t2, 10 # R[7]=10
loop_head:
bge t0, t2, loop_end
# Repeated code goes here
addi t0, t0, 1 # PC=16
j loop_head
loop_end:
# R[0]=0