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RISC-V_Verilog
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2 Commits

Author SHA1 Message Date
brice.boisson 5e93084239 Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench 2023-11-28 14:24:30 +09:00
brice.boisson d51ea5c4c8 Add: memory managing different size of opperand 2023-10-26 16:36:32 +09:00