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  • 3e1ca02fd4
         Test add module program counter (#12) main BOISSON Brice 2024-01-26 16:13:54 +0100
  • 36cb472979 Add: test PC #12 test-add-module_program_counter brice.boisson 2024-01-26 16:13:21 +0100
  • 0aae6901e3 Add: test PC brice.boisson 2024-01-26 16:12:22 +0100
  • 699b643466 Add: tb archi for module PC brice.boisson 2023-12-05 13:51:51 +0900
  • e8c7cb474d
         Fix: tb reg bank delay first test after end of reset (#11) BOISSON Brice 2023-12-05 13:54:17 +0900
  • 292eaf842a Fix: tb reg bank delay first test after end of reset #11 test-reg_bank-fix-1 brice.boisson 2023-12-05 13:53:43 +0900
  • d6f7fb498b Add: tb archi for module PC brice.boisson 2023-12-05 13:51:51 +0900
  • ca6398d1e1
         Rework: separate each step of the pipeline in a different component BOISSON Brice 2023-12-04 11:34:39 +0900
  • c7eaf3fc76 Merge branch 'multi-cycle' into multi-cycle-copy #10 brice.boisson 2023-12-04 11:28:49 +0900
  • 5d35edeb63 Rebase: fix merge issue brice.boisson 2023-12-04 11:16:24 +0900
  • 30650abce8 Rebase: add change in test from main in multi-cycle-branch brice.boisson 2023-12-04 11:02:20 +0900
  • ffa137da41 Add: binary search test source code brice.boisson 2023-12-04 09:44:24 +0900
  • a0a1b26b83
         Fix: test 4 mem val to check mem value BOISSON Brice 2023-12-04 09:43:15 +0900
  • e39c521dd4 Fix: test 4 mem val to check mem value #9 brice.boisson 2023-12-04 09:38:47 +0900
  • 29306288a7
         Fix: fix saved register on stack name BOISSON Brice 2023-12-03 22:18:09 +0900
  • ce01e2078c Fix: fix saved register on stack name #8 brice.boisson 2023-12-03 22:17:29 +0900
  • 4a91b52975
         Merge pull request #7 from BriceBoisson/test-error_message_test_exec_too_low BOISSON Brice 2023-11-30 14:44:49 +0900
  • e0b2ada62f Add: error message when the number of ran test is lower than the number of test present is the assmbly file (the number of ran test can be superior, and in few time lower that's why it's only a warning #7 brice.boisson 2023-11-30 14:43:01 +0900
  • d279fe6556
         Merge pull request #6 from BriceBoisson/test-syracuse BOISSON Brice 2023-11-30 14:15:31 +0900
  • db135f06b4 Add: syracuse test source code #6 brice.boisson 2023-11-30 14:14:53 +0900
  • cd6972af6d Add: archi and comment in top level | Fix: missing var declaration in reg test bench brice.boisson 2023-11-29 11:30:58 +0900
  • 3007868c1a Add: debug command in Makefile brice.boisson 2023-11-29 11:14:42 +0900
  • fb95d74cd7 Fix: 3rd test lower test value range | clean code brice.boisson 2023-11-29 11:11:44 +0900
  • 479f110cd7 Add: power test source code brice.boisson 2023-11-29 10:39:48 +0900
  • 5e93084239 Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench brice.boisson 2023-11-28 14:24:30 +0900
  • 91514de821 Add: loop and multiplication source code test | expend instruction memory size | Fix: on empty test file brice.boisson 2023-11-27 14:27:09 +0900
  • f6b6e0f285 Fix: name of tag in branch test source code brice.boisson 2023-11-27 09:55:06 +0900
  • 8b5faa374b Add: neg branch test brice.boisson 2023-11-27 09:47:38 +0900
  • 9750e1ab48 Add: branch source code test file | Fix: remove test source code test file brice.boisson 2023-11-27 09:35:14 +0900
  • 0cf217ff7b Add: test source code for branch instruction brice.boisson 2023-11-26 22:31:27 +0900
  • c6ffe7e2e9 Fix: dynamique test bench else cond brice.boisson 2023-11-26 22:22:16 +0900
  • 9d82414a58 Fix: remove print in gen_test.py brice.boisson 2023-11-26 22:08:00 +0900
  • 0fa44c1830
         Merge pull request #5 from BriceBoisson/test-3 BOISSON Brice 2023-11-25 23:19:04 +0900
  • 7949850418 Add: new test source code + Fix: gen_bin script and bin path #5 brice.boisson 2023-11-25 23:18:24 +0900
  • 38d35c3a63
         Update README.md BOISSON Brice 2023-11-25 19:48:46 +0900
  • 0a032b36b0 Add: test command readme brice.boisson 2023-11-25 19:46:58 +0900
  • 8920eb9aba
         Merge pull request #4 from BriceBoisson/test-2 BOISSON Brice 2023-11-25 19:39:46 +0900
  • ca6d23450d Fix: divide by 4 on entry test too #4 brice.boisson 2023-11-25 19:38:14 +0900
  • c6292d3b4f Add: use space more efficiently on test datastructure brice.boisson 2023-11-25 19:34:07 +0900
  • 86abae02eb Add: name of the dynamic test following the tested element brice.boisson 2023-11-25 19:28:17 +0900
  • 9ac36fa030 Fix: clean environment between two test brice.boisson 2023-11-24 19:47:36 +0900
  • 2fa5a5dc60 Fix: remove work between two test brice.boisson 2023-11-24 19:42:21 +0900
  • 9361c493c4 Fix: Model Sim Warning Message brice.boisson 2023-11-24 19:41:40 +0900
  • ed1220978f Add: test name brice.boisson 2023-11-24 19:38:08 +0900
  • 81268259ff Add: Formating test output brice.boisson 2023-11-24 19:28:08 +0900
  • 82474c8d16 Fix: delete old folder brice.boisson 2023-11-23 13:47:03 +0900
  • 6f4f7f6969 Add: new make way enabling multiple asm generated test brice.boisson 2023-11-22 11:35:08 +0900
  • e2ca11548c Add: generate file on make brice.boisson 2023-11-21 18:45:25 +0900
  • 7d60960831 Add: generate test from comment in assembly file brice.boisson 2023-11-21 18:36:10 +0900
  • b95e79edc4 Fix: test after imm fix brice.boisson 2023-11-20 22:47:10 +0900
  • deff1ee2f7
         Merge pull request #3 from BriceBoisson/test BOISSON Brice 2023-11-20 22:31:13 +0900
  • 1f9a8ceebf Add: first test #3 brice.boisson 2023-11-20 22:30:19 +0900
  • ea75ab9206 Fix: imm value building brice.boisson 2023-11-20 22:21:41 +0900
  • 99399cd9b3 Add: test from gcc brice.boisson 2023-11-20 22:20:42 +0900
  • 93cb91f022 Add: script brice.boisson 2023-11-20 14:21:26 +0900
  • 89a66cd244 Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem) brice.boisson 2023-10-27 12:46:13 +0900
  • ae0d20b5e7 Add: change progression status brice.boisson 2023-10-26 17:43:49 +0900
  • 9613e2566e Add: risc-v test bubble sort brice.boisson 2023-10-26 17:43:00 +0900
  • d51ea5c4c8 Add: memory managing different size of opperand brice.boisson 2023-10-26 16:36:32 +0900
  • db5d909402 Add: begining bubble sort test | Fix: branch and imm value extension brice.boisson 2023-10-25 11:07:19 +0900
  • a15dc204e5 Fix: synthax brice.boisson 2023-10-25 09:03:02 +0900
  • 9c151ccbb2 Fix: readme checkbox 2 brice.boisson 2023-10-25 09:02:19 +0900
  • 298e14be54 Fix: readme checkbox brice.boisson 2023-10-25 09:01:54 +0900
  • 3eb7603cd0 Add: new infos in the readme brice.boisson 2023-10-25 09:00:42 +0900
  • a815601b50
         Merge pull request #2 from BriceBoisson/risc-v BOISSON Brice 2023-10-24 21:53:08 +0900
  • 67c71565c0 Fix: memory addressing 32 to 8 bits #2 brice.boisson 2023-10-24 21:52:07 +0900
  • 4d0d7489cb
         Merge pull request #1 from BriceBoisson/risc-v BOISSON Brice 2023-10-24 21:20:46 +0900
  • 0fb4170797 Add: tb_risc_v fibonacci compute #1 brice.boisson 2023-10-24 21:19:24 +0900
  • 7c1a871e99 Add: tb registers bank brice.boisson 2023-10-24 20:08:36 +0900
  • ecfb4a9cc5 Fix: change alu op_code to func brice.boisson 2023-10-24 19:39:42 +0900
  • 6cc27cdc2f Add: tb alu all func brice.boisson 2023-10-24 19:36:34 +0900
  • b99914f42d Add: named parameter for ALU func | alu test case brice.boisson 2023-10-24 10:49:29 +0900
  • 5829400fea Add: tb macro to assert brice.boisson 2023-10-23 17:34:37 +0900
  • 72d688018b Fix: clean name [3] brice.boisson 2023-10-23 14:15:21 +0900
  • 2c9abe91af Fix: clean name [2] brice.boisson 2023-10-23 11:47:43 +0900
  • c1a099c75d Fix: remove useless control signal brice.boisson 2023-10-23 11:37:10 +0900
  • dc087b24f2 Add: set R[0] to 0 brice.boisson 2023-10-23 11:32:25 +0900
  • 44ac59210c Fix: clean name [1] brice.boisson 2023-10-23 11:24:09 +0900
  • 57216f7c85 Fix: use parameter to name op code brice.boisson 2023-10-23 10:10:49 +0900
  • 54e3ecdfa3 Fix: set right value alu auipc brice.boisson 2023-10-23 09:50:51 +0900
  • 766f77fa6c Add: sign extension - cpu is now able to compute fibonacci brice.boisson 2023-10-23 09:41:40 +0900
  • 33835ec0ed Fix: reset edge brice.boisson 2023-10-22 22:41:39 +0900
  • f717284c47 Add: assembly of risc-v cpu brice.boisson 2023-10-21 22:57:58 +0900
  • b3fd2a827d Add: basic element for risc-v single cycle cpu brice.boisson 2023-10-20 18:48:18 +0900
  • 0e72c3a2e6 Add: Makefile brice.boisson 2023-10-11 17:43:36 +0900
  • 83286df734 Add: Archi brice.boisson 2023-10-10 16:20:01 +0900
  • 4ded2be172 Add: README brice.boisson 2023-10-10 16:17:16 +0900
  • 4949d1f96e Add: Archi brice.boisson 2023-10-10 16:13:26 +0900