5 Commits

Author	SHA1	Message	Date
brice.boisson	57216f7c85	Fix: use parameter to name op code	2023-10-23 10:10:49 +09:00
brice.boisson	54e3ecdfa3	Fix: set right value alu auipc	2023-10-23 09:50:51 +09:00
brice.boisson	766f77fa6c	Add: sign extension - cpu is now able to compute fibonacci	2023-10-23 09:41:40 +09:00
brice.boisson	f717284c47	Add: assembly of risc-v cpu	2023-10-21 22:57:58 +09:00
brice.boisson	b3fd2a827d	Add: basic element for risc-v single cycle cpu	2023-10-20 18:48:18 +09:00