5 Commits

Author	SHA1	Message	Date
brice.boisson	89a66cd244	Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)	2023-10-27 12:46:13 +09:00
brice.boisson	72d688018b	Fix: clean name [3]	2023-10-23 14:15:21 +09:00
brice.boisson	44ac59210c	Fix: clean name [1]	2023-10-23 11:24:09 +09:00
brice.boisson	33835ec0ed	Fix: reset edge	2023-10-22 22:41:39 +09:00
brice.boisson	b3fd2a827d	Add: basic element for risc-v single cycle cpu	2023-10-20 18:48:18 +09:00