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merge into: brice/RISC-V_Verilog:test-add-module_program_counter
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brice/RISC-V_Verilog:main brice/RISC-V_Verilog:test-add-module_program_counter brice/RISC-V_Verilog:test-reg_bank-fix-1
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pull from: brice/RISC-V_Verilog:test-add-module_program_counter
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brice/RISC-V_Verilog:main brice/RISC-V_Verilog:test-add-module_program_counter brice/RISC-V_Verilog:test-reg_bank-fix-1
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