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Divide by 4 instruction address to use space more efficiently #4

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BriceBoisson merged 2 commits from test-2 into main 2023-11-25 10:39:46 +00:00
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BriceBoisson commented 2023-11-25 10:39:35 +00:00 (Migrated from github.com)
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Reference: brice/RISC-V_Verilog#4
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