brice
/
RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Divide by 4 instruction address to use space more efficiently #4

Merged
BriceBoisson merged 2 commits from test-2 into main 2023-11-25 10:39:46 +00:00
Conversation 0 Commits 2 Files Changed 1 +4 -2

2 Commits

Author SHA1 Message Date
brice.boisson ca6d23450d Fix: divide by 4 on entry test too 2023-11-25 19:38:14 +09:00
brice.boisson c6292d3b4f Add: use space more efficiently on test datastructure 2023-11-25 19:34:07 +09:00