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RISC-V_Verilog
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RISC-V base implementation #1

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BriceBoisson merged 17 commits from risc-v into main 2023-10-24 12:20:46 +00:00
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2 changed files with 36 additions and 42 deletions
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44
rtl/decoder.v
View File

@ -6,8 +6,8 @@ module decoder (input [31:0] instruction,
output reg alu_src,
output reg [3:0] alu_func,
output reg mem_we,
output reg [1:0] jmp_pc,
output reg b_pc, alu_not);
output reg [1:0] pc_is_branch,
output reg pc_is_jmp, alu_not);
`include "op_code.vh"
@ -88,8 +88,8 @@ endfunction
alu_src = 0;
alu_func = get_alu_func(instruction[14:12], instruction[30]);
mem_we = 0;
jmp_pc = 2'b00;
b_pc = 0;
pc_is_branch = 2'b00;
pc_is_jmp = 0;
alu_not = 0;
end
OP_IMM : begin // OP-IMM - Addi, ...
@ -103,8 +103,8 @@ endfunction
alu_src = 1;
alu_func = get_alu_func_imm(instruction[14:12], instruction[30]);
mem_we = 0;
jmp_pc = 2'b00;
b_pc = 0;
pc_is_branch = 2'b00;
pc_is_jmp = 0;
alu_not = 0;
end
LOAD : begin // LOAD - Lw, ...
@ -118,8 +118,8 @@ endfunction
alu_src = 1;
alu_func = 3'b000;
mem_we = 0;
jmp_pc = 2'b00;
b_pc = 0;
pc_is_branch = 2'b00;
pc_is_jmp = 0;
alu_not = 0;
end
STORE : begin // STORE - Sw, ...
@ -133,8 +133,8 @@ endfunction
alu_src = 1;
alu_func = 3'b000;
mem_we = 1;
jmp_pc = 2'b00;
b_pc = 0;
pc_is_branch = 2'b00;
pc_is_jmp = 0;
alu_not = 0;
end
BRANCH : begin // BRANCH - Beq, ...
@ -148,8 +148,8 @@ endfunction
alu_src = 0;
alu_func = branch_op_code(instruction[14:12]);
mem_we = 0;
jmp_pc = 2'b00;
b_pc = 1;
pc_is_branch = 2'b00;
pc_is_jmp = 1;
alu_not = branch_not(instruction[14:12]);
end
JAL : begin // JUMP - Jal
@ -163,8 +163,8 @@ endfunction
alu_src = 0;
alu_func = 3'b000;
mem_we = 0;
jmp_pc = 2'b01;
b_pc = 0;
pc_is_branch = 2'b01;
pc_is_jmp = 0;
alu_not = 0;
end
JALR : begin // JUMP REG - Jalr
@ -178,8 +178,8 @@ endfunction
alu_src = 0;
alu_func = 3'b000;
mem_we = 0;
jmp_pc = 2'b10;
b_pc = 0;
pc_is_branch = 2'b10;
pc_is_jmp = 0;
alu_not = 0;
end
LUI : begin // LUI - lui
@ -192,8 +192,8 @@ endfunction
alu_src = 1;
alu_func = 3'b000;
mem_we = 0;
jmp_pc = 2'b00;
b_pc = 0;
pc_is_branch = 2'b00;
pc_is_jmp = 0;
alu_not = 0;
end
AUIPC : begin // AUIPC - auipc
@ -206,8 +206,8 @@ endfunction
alu_src = 1;
alu_func = 3'b000;
mem_we = 0;
jmp_pc = 2'b00;
b_pc = 0;
pc_is_branch = 2'b00;
pc_is_jmp = 0;
alu_not = 0;
end
default : begin // NOP
@ -220,8 +220,8 @@ endfunction
alu_src = 0;
alu_func = 3'b000;
mem_we = 0;
jmp_pc = 2'b00;
b_pc = 0;
pc_is_branch = 2'b00;
pc_is_jmp = 0;
alu_not = 0;
end
endcase

32
rtl/risc_v_cpu.v
View File

@ -1,30 +1,24 @@
module risc_v_cpu (input clock, reset, output [31:0] out);
wire alu_src, alu_not;
wire [3:0] alu_func;
wire [31:0] alu_in_b, alu_out;
wire [31:0] instruction;
wire [31:0] imm;
wire reg_we;
wire [1:0] reg_sel_data_in;
wire [4:0] reg_sel_out_a, reg_sel_out_b, reg_sel_in;
wire [31:0] reg_data_out_a, reg_data_out_b, reg_data_in;
wire [31:0] instruction;
wire alu_src, alu_not;
wire [3:0] alu_func;
wire [31:0] alu_in_b, alu_out;
wire mem_we;
wire [31:0] mem_out;
wire [1:0] jmp_pc;
wire b_pc;
wire [31:0] imm;
wire [1:0] pc_sel_in;
wire [31:0] pc_addr;
wire [31:0] pc_new_addr;
wire [31:0] pc_store;
wire pc_is_jmp;
wire [1:0] pc_is_branch, pc_sel_in;
wire [31:0] pc_addr, pc_new_addr;
decoder decoder (
.instruction(instruction),
@ -37,8 +31,8 @@ module risc_v_cpu (input clock, reset, output [31:0] out);
.alu_src(alu_src),
.alu_func(alu_func),
.mem_we(mem_we),
.jmp_pc(jmp_pc),
.b_pc(b_pc),
.pc_is_branch(pc_is_branch),
.pc_is_jmp(pc_is_jmp),
.alu_not(alu_not)
);
@ -69,9 +63,9 @@ module risc_v_cpu (input clock, reset, output [31:0] out);
);
mux2_1 #(2) mux2_1_2 (
.A(jmp_pc),
.A(pc_is_branch),
.B({alu_out[1], (alu_not ? ~alu_out[0] : alu_out[0])}),
.S(b_pc),
.S(pc_is_jmp),
.O(pc_sel_in)
);