tb/tb_alu.v

@@ -1,9 +1,10 @@
 `timescale 1ns / 1ps
+`include "tb_tools.vh"
 
 module tb_alu ();
     reg  [31:0] in_a;
     reg  [31:0] in_b;
-    reg  [2:0]  op_code;
+    reg  [3:0]  op_code;
     wire [31:0] out;
 
     alu alu (
@@ -14,23 +15,18 @@ module tb_alu ();
     );
 
     initial begin
-        $monitor("time=%3d, in_a=%d, in_b=%d, ctrl=%b, q=%d \n",
+        in_a = 32'b0;
-                    $time, in_a, in_b, op_code, out);
+        in_b = 32'b0;
+        op_code = 4'b0000;
+        `assert("alu : 0 + 0", out, 0)
+        in_a = 32'b1;
+        `assert("alu : 1 + 0", out, 1)
+        in_b = 32'b1;
+        `assert("alu : 1 + 1", out, 2)
+        op_code = 4'b0001;
+        `assert("alu : 1 - 1", out, 0)
 
-        in_a = 1'b0;
+        `end_message
-        in_b = 1'b0;
-        op_code = 3'b000;
-        #20
-        if (out !== 0) $display("[FAILED] output should be 0");
-        in_a = 1'b1;
-        #20
-        if (out !== 1) $display("[FAILED] output should be 1");
-        in_b = 1'b1;
-        #20
-        if (out !== 2) $display("[FAILED] output should be 2");
-        op_code = 3'b001;
-        #20
-        if (out !== 2) $display("[FAILED] output should be 2");
     end
 
 endmodule : tb_alu

tb/tb_mux2_1.v

@@ -1,39 +1,39 @@
 `timescale 1ns / 1ps
+`include "tb_tools.vh"
 
 module tb_mux2_1 ();
-    reg         ctrl;
+
-    reg  [31:0] in_a;
+    reg         sel;
-    reg  [31:0] in_b;
+    reg  [31:0] in_1;
+    reg  [31:0] in_2;
     wire [31:0] out;
 
     mux2_1 mux (
-        .S(ctrl),
+        .in_1(in_1),
-        .A(in_a),
+        .in_2(in_2),
-        .B(in_b),
+        .sel(sel),
-        .O(out)
+        .out(out)
     );
 
     initial begin
-        $monitor("time=%3d, in_a=%d, in_b=%d, ctrl=%b, q=%d \n",
+        in_1 = 1'b0;
-                    $time, in_a, in_b, ctrl, out);
+        in_2 = 1'b0;
+        sel = 1'b0;
+        `assert("mux in_1: 0, in_2: 0, sel: 0", out, 0)
+        in_1 = 1'b1;
+        `assert("mux in_1: 1, in_2: 0, sel: 0", out, 1)
+        sel = 1'b1;
+        `assert("mux in_1: 1, in_2: 0, sel: 1", out, 0)
+        in_2 = 1'b1;
+        `assert("mux in_1: 1, in_2: 1, sel: 1", out, 1)
+        in_1 = 1'b0;
+        `assert("mux in_1: 0, in_2: 1, sel: 1", out, 1)
+        in_2 = 1'b0;
+        `assert("mux in_1: 0, in_2: 0, sel: 1", out, 0)
+        sel = 1'b0;
+        `assert("mux in_1: 0, in_2: 0, sel: 0", out, 0)
 
-        in_a = 1'b0;
+        `end_message
-        in_b = 1'b0;
-        ctrl = 1'b0;
-        #20
-        if (out !== 0) $display("[FAILED] output should be 0");
-        in_a = 1'b1;
-        #20
-        if (out !== 1) $display("[FAILED] output should be 1");
-        ctrl = 1'b1;
-        in_a = 1'b0;
-        in_b = 1'b1;
-        #20
-        if (out !== 1) $display("[FAILED] output should be 1");
-        ctrl = 1'b0;
-        in_a = 1'b1;
-        #20
-        if (out !== 1) $display("[FAILED] output should be 1");
     end
 
 endmodule : tb_mux2_1

tb/tb_risc_v_cpu.v

@@ -1,4 +1,5 @@
 `timescale 1ns / 1ps
+`include "tb_tools.vh"
 
 module tb_risc_v_cpu ();
     reg         clk;

tb/tb_tools.vh

@@ -0,0 +1,7 @@
+`define assert(message, expected, got) \
+    #20 \
+    if(expected !== got) begin \
+        $display("\033[0;31m[FAILED]\033[0m : %s - got: %d, expected: %d", message, expected, got); \
+    end
+
+`define end_message $display("\033[0;32mIf no \033[0m[FAILED]\033[0;32m messages, all tests passed!\033[0m");