33 lines
629 B
Verilog
33 lines
629 B
Verilog
`timescale 1ns / 1ps
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`include "tb_tools.vh"
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module tb_alu ();
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reg [31:0] in_a;
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reg [31:0] in_b;
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reg [3:0] op_code;
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wire [31:0] out;
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alu alu (
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.in_a(in_a),
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.in_b(in_b),
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.op_code(op_code),
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.out(out)
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);
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initial begin
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in_a = 32'b0;
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in_b = 32'b0;
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op_code = 4'b0000;
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`assert("alu : 0 + 0", out, 0)
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in_a = 32'b1;
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`assert("alu : 1 + 0", out, 1)
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in_b = 32'b1;
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`assert("alu : 1 + 1", out, 2)
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op_code = 4'b0001;
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`assert("alu : 1 - 1", out, 0)
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`end_message
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end
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endmodule : tb_alu
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