brice/RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Rework: separate each step of the pipeline in a different component #10

Merged
BriceBoisson merged 4 commits from multi-cycle into main 2023-12-04 02:34:39 +00:00
Conversation 0 Commits 4 Files Changed 8
+179 -115

4 Commits

Author SHA1 Message Date
brice.boisson c7eaf3fc76 Merge branch 'multi-cycle' into multi-cycle-copy 2023-12-04 11:28:49 +09:00
brice.boisson 5d35edeb63 Rebase: fix merge issue 2023-12-04 11:16:24 +09:00
brice.boisson 30650abce8 Rebase: add change in test from main in multi-cycle-branch 2023-12-04 11:02:20 +09:00
brice.boisson 89a66cd244 Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem) 2023-10-27 12:46:13 +09:00