brice
/
RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix: fix saved register on stack name #8

Merged
BriceBoisson merged 1 commits from test-syracuse-2 into main 2023-12-03 13:18:09 +00:00
Conversation 0 Commits 1 Files Changed 1 +1 -1
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tb/test_source_code/tb_risc_v_cpu/syracuse.S
View File

@ -46,7 +46,7 @@ sw a1, 8(sp)
sw s0, 12(sp) sw s0, 12(sp)
sw s1, 16(sp) sw s1, 16(sp)
sw s2, 20(sp) sw s2, 20(sp)
sw s2, 24(sp) sw s3, 24(sp)
addi sp, sp, 24 addi sp, sp, 24
add s1, a1, zero add s1, a1, zero
li s0, 0 li s0, 0