BOISSON Brice ca6398d1e1 Rework: separate each step of the pipeline in a different component

2023-12-04 11:34:39 +09:00

..

alu_func.vh

Add: named parameter for ALU func | alu test case

2023-10-24 10:49:29 +09:00

alu.v

Fix: change alu op_code to func

2023-10-24 19:39:42 +09:00

decoder.v

Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench

2023-11-28 14:24:30 +09:00

instruction.v

Add: power test source code

2023-11-29 10:39:48 +09:00

mem_func.vh

Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench

2023-11-28 14:24:30 +09:00

memory.v

Add: power test source code

2023-11-29 10:39:48 +09:00

module_alu.v

Rework: separate each step of the pipeline in a different component

2023-12-04 11:34:39 +09:00

module_program_counter.v

Rework: separate each step of the pipeline in a different component

2023-12-04 11:34:39 +09:00

module_registers_bank.v

Rework: separate each step of the pipeline in a different component

2023-12-04 11:34:39 +09:00

mux2_1.v

Fix: clean name [3]

2023-10-23 14:15:21 +09:00

mux4_1.v

Fix: clean name [3]

2023-10-23 14:15:21 +09:00

op_code.vh

Fix: use parameter to name op code

2023-10-23 10:10:49 +09:00

program_counter.v

Rework: separate each step of the pipeline in a different component

2023-12-04 11:34:39 +09:00

registers_bank.v

Fix: clean name [3]

2023-10-23 14:15:21 +09:00

risc_v_cpu_top.v

Add: archi and comment in top level | Fix: missing var declaration in reg test bench

2023-11-29 11:30:58 +09:00

risc_v_cpu.v

Rework: separate each step of the pipeline in a different component

2023-12-04 11:34:39 +09:00