brice/RISC-V_Verilog
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brice.boisson 0fb4170797 Add: tb_risc_v fibonacci compute
2023-10-24 21:19:24 +09:00
rtl
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Add: basic element for risc-v single cycle cpu
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README.md
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README.md

This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.

Description
No description provided
Readme 127 KiB
Languages
Verilog 75.1%
Assembly 10.9%
Shell 5.6%
SystemVerilog 5.1%
Python 2.9%
Other 0.4%