RISC-V Verilog

This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.

This CPU will implement the RV32I ISA, with the following goal:

• [] Single cycle RISC-V RVI32I CPU
• [] Multi cycle CPU
• [] Pipelining
• [] (Bonus) RISC-V privileged ISA