8 lines
301 B
Markdown
8 lines
301 B
Markdown
# RISC-V Verilog
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This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.
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This CPU will implement the RV32I ISA, with the following goal:
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[] Single cycle RISC-V RVI32I CPU
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[] Multi cycle CPU
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[] Pipelining
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[] (Bonus) RISC-V privileged ISA |