brice.boisson 54e3ecdfa3 Fix: set right value alu auipc

2023-10-23 09:50:51 +09:00

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alu.v

Add: assembly of risc-v cpu

2023-10-21 22:57:58 +09:00

decoder.v

Fix: set right value alu auipc

2023-10-23 09:50:51 +09:00

instruction.v

Add: sign extension - cpu is now able to compute fibonacci

2023-10-23 09:41:40 +09:00

memory.v

Fix: reset edge

2023-10-22 22:41:39 +09:00

mux2_1.v

Add: assembly of risc-v cpu

2023-10-21 22:57:58 +09:00

mux4_1.v

Fix: reset edge

2023-10-22 22:41:39 +09:00

program_counter.v

Fix: reset edge

2023-10-22 22:41:39 +09:00

registers_bank.v

Fix: reset edge

2023-10-22 22:41:39 +09:00

risc_v_cpu.v

Fix: set right value alu auipc

2023-10-23 09:50:51 +09:00

risc-v_cpu_top.v

Add: Archi

2023-10-10 16:13:26 +09:00