13 lines
275 B
Verilog
13 lines
275 B
Verilog
module program_counter (input clock, reset,
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input [31:0] new_pc,
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output reg [31:0] pc);
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always @ (posedge clock, posedge reset) begin
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if (reset == 1'b1)
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pc <= 32'b0;
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else
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pc <= new_pc;
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end
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endmodule
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