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RISC-V_Verilog
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brice.boisson 5829400fea Add: tb macro to assert 2023-10-23 17:34:37 +09:00
rtl Fix: clean name [3] 2023-10-23 14:15:21 +09:00
scripts Add: basic element for risc-v single cycle cpu 2023-10-20 18:48:18 +09:00
sim Add: Makefile 2023-10-11 17:43:36 +09:00
tb Add: tb macro to assert 2023-10-23 17:34:37 +09:00
.gitignore Add: README 2023-10-10 16:17:16 +09:00
Makefile Add: Makefile 2023-10-11 17:43:36 +09:00
README.md Add: README 2023-10-10 16:17:16 +09:00

README.md

This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.