21 lines
630 B
Verilog
21 lines
630 B
Verilog
module alu (input [31:0] in_a, in_b,
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input [3:0] op_code,
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output reg [31:0] out);
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always@ (*) begin
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case (op_code)
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4'b0000 : out <= in_a + in_b;
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4'b0001 : out <= in_a - in_b;
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4'b0010 : out <= in_a << in_b;
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4'b0011 : out <= (in_a < in_b) ? 1 : 0;
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4'b0100 : out <= in_a ^ in_b;
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4'b0101 : out <= in_a >> in_b;
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4'b0111 : out <= in_a >>> in_b;
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4'b1000 : out <= in_a | in_b;
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4'b1001 : out <= in_a & in_b;
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default : out <= 32'b0;
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endcase
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end
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endmodule
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