54 lines
1.5 KiB
Verilog
54 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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`include "tb_tools.vh"
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module tb_mux4_1 ();
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reg [1:0] sel;
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reg [31:0] in_1;
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reg [31:0] in_2;
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reg [31:0] in_3;
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reg [31:0] in_4;
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wire [31:0] out;
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mux4_1 mux (
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.in_1(in_1),
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.in_2(in_2),
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.in_3(in_3),
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.in_4(in_4),
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.sel(sel),
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.out(out)
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);
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initial begin
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in_1 = 1'b0;
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in_2 = 1'b0;
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in_3 = 1'b0;
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in_4 = 1'b0;
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sel = 2'b00;
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`assert("mux in_1: 0, in_2: 0, in_3: 0, in_4: 0, sel: 0", out, 0)
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in_1 = 1'b1;
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`assert("mux in_1: 1, in_2: 0, in_3: 0, in_4: 0, sel: 0", out, 1)
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sel = 2'b01;
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`assert("mux in_1: 1, in_2: 0, in_3: 0, in_4: 0, sel: 1", out, 0)
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in_2 = 1'b1;
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`assert("mux in_1: 1, in_2: 1, in_3: 0, in_4: 0, sel: 1", out, 1)
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sel = 2'b10;
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`assert("mux in_1: 1, in_2: 0, in_3: 0, in_4: 0, sel: 2", out, 0)
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in_3 = 1'b1;
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`assert("mux in_1: 1, in_2: 1, in_3: 1, in_4: 0, sel: 2", out, 1)
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sel = 2'b11;
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`assert("mux in_1: 1, in_2: 0, in_3: 1, in_4: 0, sel: 3", out, 0)
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in_4 = 1'b1;
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`assert("mux in_1: 1, in_2: 1, in_3: 1, in_4: 1, sel: 3", out, 1)
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in_1 = 1'b0;
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`assert("mux in_1: 0, in_2: 1, in_3: 1, in_4: 1, sel: 1", out, 1)
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in_2 = 1'b0;
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`assert("mux in_1: 0, in_2: 0, in_3: 1, in_4: 1, sel: 1", out, 1)
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sel = 2'b00;
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`assert("mux in_1: 0, in_2: 0, in_3: 1, in_4: 1, sel: 0", out, 0)
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`end_message
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end
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endmodule : tb_mux4_1
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