brice.boisson 5e93084239 Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench		2023-11-28 14:24:30 +09:00
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test_source_code/tb_risc_v_cpu	Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench	2023-11-28 14:24:30 +09:00
tb_alu.v	Fix: change alu op_code to func	2023-10-24 19:39:42 +09:00
tb_mux2_1.v	Add: tb macro to assert	2023-10-23 17:34:37 +09:00
tb_mux4_1.v	Add: tb registers bank	2023-10-24 20:08:36 +09:00
tb_registers_bank.v	Add: risc-v test bubble sort	2023-10-26 17:43:00 +09:00
tb_risc_v_cpu-dyn.v	Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench	2023-11-28 14:24:30 +09:00
tb_risc_v_cpu.v	Fix: test after imm fix	2023-11-20 22:47:10 +09:00
tb_tools.vh	Add: name of the dynamic test following the tested element	2023-11-25 19:28:17 +09:00