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5e93084239569b4beed92996f41c4e86ad4d4018
RISC-V_Verilog/tb/test_source_code/tb_risc_v_cpu
History
brice.boisson 5e93084239 Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench
2023-11-28 14:24:30 +09:00
..
alu_instruction.S
Add: new test source code + Fix: gen_bin script and bin path
2023-11-25 23:18:24 +09:00
branch_instruction.S
Fix: name of tag in branch test source code
2023-11-27 09:55:06 +09:00
loop.S
Add: loop and multiplication source code test | expend instruction memory size | Fix: on empty test file
2023-11-27 14:27:09 +09:00
multiplication.S
Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench
2023-11-28 14:24:30 +09:00
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