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alu.v
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Fix: change alu op_code to func
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2023-10-24 19:39:42 +09:00 |
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alu_func.vh
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Add: named parameter for ALU func | alu test case
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2023-10-24 10:49:29 +09:00 |
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decoder.v
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Add: risc-v test bubble sort
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2023-10-26 17:43:00 +09:00 |
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instruction.v
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Add: begining bubble sort test | Fix: branch and imm value extension
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2023-10-25 11:07:19 +09:00 |
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mem_func.vh
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Add: memory managing different size of opperand
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2023-10-26 16:36:32 +09:00 |
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memory.v
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Add: memory managing different size of opperand
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2023-10-26 16:36:32 +09:00 |
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module_alu.v
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Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)
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2023-10-27 12:46:13 +09:00 |
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module_program_counter.v
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Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)
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2023-10-27 12:46:13 +09:00 |
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module_registers_bank.v
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Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)
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2023-10-27 12:46:13 +09:00 |
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mux2_1.v
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Fix: clean name [3]
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2023-10-23 14:15:21 +09:00 |
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mux4_1.v
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Fix: clean name [3]
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2023-10-23 14:15:21 +09:00 |
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op_code.vh
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Fix: use parameter to name op code
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2023-10-23 10:10:49 +09:00 |
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program_counter.v
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Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)
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2023-10-27 12:46:13 +09:00 |
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registers_bank.v
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Fix: clean name [3]
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2023-10-23 14:15:21 +09:00 |
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risc-v_cpu_top.v
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Add: Archi
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2023-10-10 16:13:26 +09:00 |
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risc_v_cpu.v
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Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)
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2023-10-27 12:46:13 +09:00 |
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