brice.boisson c1a099c75d Fix: remove useless control signal

2023-10-23 11:37:10 +09:00

..

alu.v

Add: assembly of risc-v cpu

2023-10-21 22:57:58 +09:00

decoder.v

Fix: remove useless control signal

2023-10-23 11:37:10 +09:00

instruction.v

Add: sign extension - cpu is now able to compute fibonacci

2023-10-23 09:41:40 +09:00

memory.v

Fix: reset edge

2023-10-22 22:41:39 +09:00

mux2_1.v

Add: assembly of risc-v cpu

2023-10-21 22:57:58 +09:00

mux4_1.v

Fix: reset edge

2023-10-22 22:41:39 +09:00

op_code.vh

Fix: use parameter to name op code

2023-10-23 10:10:49 +09:00

program_counter.v

Fix: clean name [1]

2023-10-23 11:24:09 +09:00

registers_bank.v

Add: set R[0] to 0

2023-10-23 11:32:25 +09:00

risc_v_cpu.v

Fix: remove useless control signal

2023-10-23 11:37:10 +09:00

risc-v_cpu_top.v

Add: Archi

2023-10-10 16:13:26 +09:00