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d6f7fb498b1347201d1c08f9c368aff27a10a77f
RISC-V_Verilog/tb
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brice.boisson d6f7fb498b Add: tb archi for module PC
2023-12-05 13:51:51 +09:00
..
test_source_code/tb_risc_v_cpu
Add: binary search test source code
2023-12-04 09:44:24 +09:00
tb_alu.v
Fix: change alu op_code to func
2023-10-24 19:39:42 +09:00
tb_module_program_counter.v
Add: tb archi for module PC
2023-12-05 13:51:51 +09:00
tb_mux2_1.v
Add: tb macro to assert
2023-10-23 17:34:37 +09:00
tb_mux4_1.v
Add: tb registers bank
2023-10-24 20:08:36 +09:00
tb_registers_bank.v
Add: archi and comment in top level | Fix: missing var declaration in reg test bench
2023-11-29 11:30:58 +09:00
tb_risc_v_cpu-dyn.v
Rework: separate each step of the pipeline in a different component
2023-12-04 11:34:39 +09:00
tb_risc_v_cpu.v
Rework: separate each step of the pipeline in a different component
2023-12-04 11:34:39 +09:00
tb_tools.vh
Rework: separate each step of the pipeline in a different component
2023-12-04 11:34:39 +09:00
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