brice/RISC-V_Verilog
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brice.boisson ecfb4a9cc5 Fix: change alu op_code to func
2023-10-24 19:39:42 +09:00
rtl
Fix: change alu op_code to func
2023-10-24 19:39:42 +09:00
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Add: basic element for risc-v single cycle cpu
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Fix: change alu op_code to func
2023-10-24 19:39:42 +09:00
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README.md

This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.

Description
No description provided
Readme 127 KiB
Languages
Verilog 75.1%
Assembly 10.9%
Shell 5.6%
SystemVerilog 5.1%
Python 2.9%
Other 0.4%