RISC-V_Verilog/Makefile

all:
	$(MAKE) -C sim $@

debug:
	$(MAKE) -C sim $@

clean:
	rm -rf sim/work
	rm -rf work
	rm -rf sim/transcript
	rm -rf transcript
	rm -rf sim/vsim.wlf
	rm -rf sim/simu.do
	rm -rf sim/*.bin
	rm -rf sim/*.elf
	rm -rf sim/*.o
	rm -rf sim/*.tmp
Add: new make way enabling multiple asm generated test 2023-11-22 02:35:08 +00:00			`all:`
Add: Makefile 2023-10-11 08:43:36 +00:00			`$(MAKE) -C sim $@`

Add: new make way enabling multiple asm generated test 2023-11-22 02:35:08 +00:00			`debug:`
Add: Makefile 2023-10-11 08:43:36 +00:00			`$(MAKE) -C sim $@`

			`clean:`
			`rm -rf sim/work`
Add: risc-v test bubble sort 2023-10-26 08:43:00 +00:00			`rm -rf work`
Add: Makefile 2023-10-11 08:43:36 +00:00			`rm -rf sim/transcript`
Add: risc-v test bubble sort 2023-10-26 08:43:00 +00:00			`rm -rf transcript`
Add: Makefile 2023-10-11 08:43:36 +00:00			`rm -rf sim/vsim.wlf`
			`rm -rf sim/simu.do`
Add: new make way enabling multiple asm generated test 2023-11-22 02:35:08 +00:00			`rm -rf sim/*.bin`
			`rm -rf sim/*.elf`
			`rm -rf sim/*.o`
			`rm -rf sim/*.tmp`