Add: README

2023-10-10 16:17:16 +09:00 · 2023-10-10 16:17:16 +09:00 · 4ded2be172
parent 4949d1f96e
commit 4ded2be172
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--- a/.gitignore
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--- a/README.md
+++ b/README.md
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+This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.
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				`This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.`