Add: risc-v test bubble sort
This commit is contained in:
brice.boisson
parent
d51ea5c4c8
commit
9613e2566e
2
Makefile
2
Makefile
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@ -9,6 +9,8 @@ simulation:
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clean:
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clean:
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rm -rf sim/work
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rm -rf sim/work
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rm -rf work
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rm -rf sim/transcript
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rm -rf sim/transcript
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rm -rf transcript
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rm -rf sim/vsim.wlf
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rm -rf sim/vsim.wlf
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rm -rf sim/simu.do
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rm -rf sim/simu.do
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@ -50,12 +50,12 @@ endfunction
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function [3:0] branch_func(input [2:0] func);
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function [3:0] branch_func(input [2:0] func);
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begin
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begin
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case (func)
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case (func)
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3'b000 : branch_func = 4'b0001;
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3'b000 : branch_func = SUB;
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3'b001 : branch_func = 4'b0001;
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3'b001 : branch_func = SUB;
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3'b010 : branch_func = 4'b0011;
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3'b100 : branch_func = SLT;
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3'b011 : branch_func = 4'b0011;
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3'b101 : branch_func = SLT;
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3'b100 : branch_func = 4'b0011;
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3'b110 : branch_func = SLTU;
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3'b101 : branch_func = 4'b0011;
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3'b111 : branch_func = SLTU;
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default : branch_func = 4'b0000;
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default : branch_func = 4'b0000;
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endcase
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endcase
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end
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end
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@ -66,10 +66,10 @@ function branch_not(input [2:0] func);
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case (func)
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case (func)
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3'b000 : branch_not = 1;
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3'b000 : branch_not = 1;
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3'b001 : branch_not = 0;
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3'b001 : branch_not = 0;
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3'b010 : branch_not = 0;
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3'b011 : branch_not = 1;
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3'b100 : branch_not = 0;
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3'b100 : branch_not = 0;
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3'b101 : branch_not = 1;
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3'b101 : branch_not = 1;
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3'b110 : branch_not = 0;
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3'b111 : branch_not = 1;
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default : branch_not = 0;
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default : branch_not = 0;
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endcase
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endcase
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end
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end
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@ -69,7 +69,7 @@ module risc_v_cpu (input clock, reset,
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mux2_1 #(2) mux2_pc_sel_branch (
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mux2_1 #(2) mux2_pc_sel_branch (
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.in_1(pc_is_branch),
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.in_1(pc_is_branch),
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.in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 0 ? 1'b1 : 1'b0))}),
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.in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
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.sel(pc_is_jmp),
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.sel(pc_is_jmp),
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.out(pc_sel_in)
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.out(pc_sel_in)
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);
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);
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@ -26,7 +26,7 @@ vlog ../tb/tb_'"$FILE_NAME"'.v
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' >> ./sim/simu.do
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' >> ./sim/simu.do
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echo 'vsim tb_'"$FILE_NAME"'
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echo 'vsim tb_'"$FILE_NAME"'
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add wave -radix unsigned *' >> ./sim/simu.do
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' >> ./sim/simu.do
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# loop through all arguments from $3
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# loop through all arguments from $3
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@ -4,7 +4,6 @@
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module tb_registers_bank ();
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module tb_registers_bank ();
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reg clk;
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reg clk;
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reg reset;
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reg reset;
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integer i;
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reg we;
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reg we;
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reg [4:0] sel_in;
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reg [4:0] sel_in;
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reg [4:0] sel_out_a;
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reg [4:0] sel_out_a;
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@ -186,30 +186,23 @@ module tb_risc_v_cpu ();
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clk = 1'b0;
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clk = 1'b0;
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/* BUBBLE SORT
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/* BUBBLE SORT
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int len = 10;
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int array[] = {10, 9, 8, 7, 6, 5, 4, 3, 2, 1};
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for (int i = len - 1; i > 0; i--)
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LOAD MEM[R[2] + 0] to R[3]
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{
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LOAD MEM[R[2] + 1] to R[4]
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for (int j = 0; j < i; j++)
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JUMP TO R[2]++ if R[4] >= R[3]
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{
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STR R[4] to MEM[R[2] + 0]
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if (array[j] > array[j + 1])
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STR R[3] to MEM[R[2] + 1]
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{
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R[2]++
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int temp = array[j];
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JUM to -12 if R[2] < R[1]
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array[j] = array[j + 1];
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R[1]--
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array[j + 1] = temp;
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JMP if R[1] == 0 FIRST LINE
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}
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}
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}
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*/
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*/
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/* BUBBLE SORT */
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/* ADDi $9, R[0], R[1] - R[1] = 9 */
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/* ADDi $10, R[0], R[1] - R[1] = 10 */
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/* "000000001010_00000_000_00001_0010000" */
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/* "000000001010_00000_000_00001_0010000" */
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risc_v_cpu.uut_instruction.memory[0] = 8'b10010000;
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risc_v_cpu.uut_instruction.memory[0] = 8'b10010000;
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risc_v_cpu.uut_instruction.memory[1] = 8'b00000000;
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risc_v_cpu.uut_instruction.memory[1] = 8'b00000000;
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risc_v_cpu.uut_instruction.memory[2] = 8'b10100000;
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risc_v_cpu.uut_instruction.memory[2] = 8'b10010000;
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risc_v_cpu.uut_instruction.memory[3] = 8'b00000000;
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risc_v_cpu.uut_instruction.memory[3] = 8'b00000000;
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/* ADDi $10, R[0], R[2] - R[2] = 10 */
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/* ADDi $10, R[0], R[2] - R[2] = 10 */
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@ -233,46 +226,120 @@ module tb_risc_v_cpu ();
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risc_v_cpu.uut_instruction.memory[14] = 8'b00100000;
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risc_v_cpu.uut_instruction.memory[14] = 8'b00100000;
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risc_v_cpu.uut_instruction.memory[15] = 8'b00000000;
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risc_v_cpu.uut_instruction.memory[15] = 8'b00000000;
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/* ADDi $-1, R[2], R[2] - R[2] = 9 */
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/* ADDi $-1, R[2], R[2] - R[2] = R[2] - 1 */
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/* "111111111111_00010_000_00010_0010000" */
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/* "111111111111_00010_000_00010_0010000" */
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risc_v_cpu.uut_instruction.memory[16] = 8'b00010000;
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risc_v_cpu.uut_instruction.memory[16] = 8'b00010000;
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risc_v_cpu.uut_instruction.memory[17] = 8'b00000001;
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risc_v_cpu.uut_instruction.memory[17] = 8'b00000001;
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risc_v_cpu.uut_instruction.memory[18] = 8'b11110001;
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risc_v_cpu.uut_instruction.memory[18] = 8'b11110001;
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risc_v_cpu.uut_instruction.memory[19] = 8'b11111111;
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risc_v_cpu.uut_instruction.memory[19] = 8'b11111111;
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/* ADDi $1, R[3], R[3] - R[3] = 1 */
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/* ADDi $1, R[3], R[3] - R[3] = R[3] + 1 */
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/* "000000000001_00011_000_00011_0010000" */
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/* "000000000001_00011_000_00011_0010000" */
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risc_v_cpu.uut_instruction.memory[20] = 8'b10010000;
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risc_v_cpu.uut_instruction.memory[20] = 8'b10010000;
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risc_v_cpu.uut_instruction.memory[21] = 8'b10000001;
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risc_v_cpu.uut_instruction.memory[21] = 8'b10000001;
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risc_v_cpu.uut_instruction.memory[22] = 8'b00010001;
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risc_v_cpu.uut_instruction.memory[22] = 8'b00010001;
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risc_v_cpu.uut_instruction.memory[23] = 8'b00000000;
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risc_v_cpu.uut_instruction.memory[23] = 8'b00000000;
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/* BNE -8, R[0], R[2] - R[2] = 9 */
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/* STR $0, R[3], R[2], MEM[R[3]] = 10 */
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/* "1111111_00010_00000_001_10111_1100000" */
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/* "0000000_00010_00011_000_00000_0100000" */
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risc_v_cpu.uut_instruction.memory[24] = 8'b01100000;
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risc_v_cpu.uut_instruction.memory[24] = 8'b00100000;
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risc_v_cpu.uut_instruction.memory[25] = 8'b00011100;
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risc_v_cpu.uut_instruction.memory[25] = 8'b10000000;
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risc_v_cpu.uut_instruction.memory[26] = 8'b00100000;
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risc_v_cpu.uut_instruction.memory[26] = 8'b00100001;
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risc_v_cpu.uut_instruction.memory[27] = 8'b11111110;
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risc_v_cpu.uut_instruction.memory[27] = 8'b00000000;
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`next_cycle
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/* BNE -12, R[0], R[2] - PC = PC - 12 */
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`next_cycle
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/* "1111111_00010_00000_001_10100_1100000" */
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`next_cycle
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risc_v_cpu.uut_instruction.memory[28] = 8'b01100000;
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`next_cycle
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risc_v_cpu.uut_instruction.memory[29] = 8'b00011010;
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`next_cycle
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risc_v_cpu.uut_instruction.memory[30] = 8'b00100000;
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`next_cycle
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risc_v_cpu.uut_instruction.memory[31] = 8'b11111110;
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`next_cycle
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`next_cycle
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/* ADDi $0, R[0], R[2] - R[2] = 0 */
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`next_cycle
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/* "000000000000_00000_000_00010_0010000" */
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`next_cycle
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risc_v_cpu.uut_instruction.memory[32] = 8'b00010000;
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`next_cycle
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risc_v_cpu.uut_instruction.memory[33] = 8'b00000001;
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`next_cycle
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risc_v_cpu.uut_instruction.memory[34] = 8'b00000000;
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`next_cycle
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risc_v_cpu.uut_instruction.memory[35] = 8'b00000000;
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`next_cycle
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`next_cycle
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/* LOAD MEM[R[2] + 0], R[3] - R[3] = 10 */
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`next_cycle
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/* "000000000000_00010_000_00011_0000000" */
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`next_cycle
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risc_v_cpu.uut_instruction.memory[36] = 8'b10000000;
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`next_cycle
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risc_v_cpu.uut_instruction.memory[37] = 8'b00000001;
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`next_cycle
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risc_v_cpu.uut_instruction.memory[38] = 8'b00000001;
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risc_v_cpu.uut_instruction.memory[39] = 8'b00000000;
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/* LOAD MEM[R[2] + 1], R[4] - R[4] = 9 */
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/* "000000000001_00010_000_00100_0000000" */
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risc_v_cpu.uut_instruction.memory[40] = 8'b00000000;
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risc_v_cpu.uut_instruction.memory[41] = 8'b00000010;
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risc_v_cpu.uut_instruction.memory[42] = 8'b00010001;
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risc_v_cpu.uut_instruction.memory[43] = 8'b00000000;
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/* BNE 12, R[4], R[3] - PC = PC + 12 */
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/* "0000000_00100_00011_100_01100_1100000" */
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risc_v_cpu.uut_instruction.memory[44] = 8'b01100000;
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risc_v_cpu.uut_instruction.memory[45] = 8'b11000110;
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risc_v_cpu.uut_instruction.memory[46] = 8'b01000001;
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risc_v_cpu.uut_instruction.memory[47] = 8'b00000000;
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/* STR $0, R[2], R[4], MEM[R[2]] = 9 */
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/* "0000000_00100_00010_000_00000_0100000" */
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risc_v_cpu.uut_instruction.memory[48] = 8'b00100000;
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risc_v_cpu.uut_instruction.memory[49] = 8'b00000000;
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risc_v_cpu.uut_instruction.memory[50] = 8'b01000001;
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risc_v_cpu.uut_instruction.memory[51] = 8'b00000000;
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/* STR $1, R[2], R[3], MEM[R[2]] = 9 */
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/* "0000000_00011_00010_000_00001_0100000" */
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risc_v_cpu.uut_instruction.memory[52] = 8'b10100000;
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risc_v_cpu.uut_instruction.memory[53] = 8'b00000000;
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risc_v_cpu.uut_instruction.memory[54] = 8'b00110001;
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risc_v_cpu.uut_instruction.memory[55] = 8'b00000000;
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/* ADDi $1, R[2], R[2] - R[2] = R[2] + 1 */
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/* "000000000001_00010_000_00010_0010000" */
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risc_v_cpu.uut_instruction.memory[56] = 8'b00010000;
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risc_v_cpu.uut_instruction.memory[57] = 8'b00000001;
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risc_v_cpu.uut_instruction.memory[58] = 8'b00010001;
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risc_v_cpu.uut_instruction.memory[59] = 8'b00000000;
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/* BNE -xx, R[1], R[2] - PC = PC - 8 */
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/* "1111111_00010_00001_001_01000_1100000" */
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risc_v_cpu.uut_instruction.memory[60] = 8'b01100000;
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risc_v_cpu.uut_instruction.memory[61] = 8'b10010100;
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risc_v_cpu.uut_instruction.memory[62] = 8'b00100000;
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risc_v_cpu.uut_instruction.memory[63] = 8'b11111110;
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/* ADDi $-1, R[1], R[1] - R[1] = R[1] - 1 */
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/* "111111111111_00001_000_00001_0010000" */
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risc_v_cpu.uut_instruction.memory[64] = 8'b10010000;
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risc_v_cpu.uut_instruction.memory[65] = 8'b10000000;
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risc_v_cpu.uut_instruction.memory[66] = 8'b11110000;
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risc_v_cpu.uut_instruction.memory[67] = 8'b11111111;
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/* BNE -36, R[0], R[1] - PC = PC - 8 */
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/* "1111111_00001_00000_001_100000_1100000" */
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risc_v_cpu.uut_instruction.memory[68] = 8'b01100000;
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risc_v_cpu.uut_instruction.memory[69] = 8'b10011110;
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risc_v_cpu.uut_instruction.memory[70] = 8'b00000000;
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risc_v_cpu.uut_instruction.memory[71] = 8'b11111100;
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for (i = 0; i < 387; i = i + 1) begin
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`next_cycle
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end
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`assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.memory.memory[0], 1)
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`assert_no_wait("BUBBLE SORT - MEM[1]: 2", risc_v_cpu.memory.memory[1], 2)
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`assert_no_wait("BUBBLE SORT - MEM[2]: 3", risc_v_cpu.memory.memory[2], 3)
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`assert_no_wait("BUBBLE SORT - MEM[3]: 4", risc_v_cpu.memory.memory[3], 4)
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`assert_no_wait("BUBBLE SORT - MEM[4]: 5", risc_v_cpu.memory.memory[4], 5)
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`assert_no_wait("BUBBLE SORT - MEM[5]: 6", risc_v_cpu.memory.memory[5], 6)
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`assert_no_wait("BUBBLE SORT - MEM[6]: 7", risc_v_cpu.memory.memory[6], 7)
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`assert_no_wait("BUBBLE SORT - MEM[7]: 8", risc_v_cpu.memory.memory[7], 8)
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`assert_no_wait("BUBBLE SORT - MEM[8]: 9", risc_v_cpu.memory.memory[8], 9)
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`assert_no_wait("BUBBLE SORT - MEM[9]: 10", risc_v_cpu.memory.memory[9], 10)
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`assert_no_wait("BUBBLE SORT - PROGRAM EXITED - PC: 76", risc_v_cpu.program_counter.pc_addr, 76)
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`end_message
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`end_message
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end
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end
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