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Merge pull request #2 from BriceBoisson/risc-v 

Fix: memory addressing 32 to 8 bits
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BOISSON Brice 2023-10-24 21:53:08 +09:00 committed by GitHub
parent 4d0d7489cb 67c71565c0
commit a815601b50
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 33 additions and 12 deletions
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4
rtl/instruction.v
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@ -1,8 +1,8 @@
module instruction (input [31:0] address, module instruction (input [31:0] address,
output [31:0] instruction); output [31:0] instruction);
reg [31:0] memory [63:0]; reg [7:0] memory [63:0];
assign instruction = memory[address]; assign instruction = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};
endmodule endmodule

11
rtl/memory.v
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@ -4,15 +4,18 @@ module memory (input clock, reset,
input [31:0] data_in, input [31:0] data_in,
output [31:0] data_out); output [31:0] data_out);
reg [63:0] memory [31:0]; reg [7:0] memory [63:0];
always @(posedge clock, posedge reset) begin always @(posedge clock, posedge reset) begin
if (reset == 1) if (reset == 1)
memory[0] <= 32'b0; memory[0] <= 8'b0;
else if (we == 1) else if (we == 1)
memory[address] <= data_in; memory[address] <= data_in[7:0];
memory[address + 1] <= data_in[15:8];
memory[address + 2] <= data_in[23:16];
memory[address + 3] <= data_in[31:24];
end end
assign data_out = memory[address]; assign data_out = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};
endmodule endmodule

30
tb/tb_risc_v_cpu.v
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@ -25,27 +25,45 @@ module tb_risc_v_cpu ();
/* ADDi $1, R[0], R[6] - R[6] = 1 */ /* ADDi $1, R[0], R[6] - R[6] = 1 */
/* "000000000001_00000_000_00110_0010000" */ /* "000000000001_00000_000_00110_0010000" */
risc_v_cpu.uut_instruction.memory[0] = 32'b00000000000100000000001100010000; risc_v_cpu.uut_instruction.memory[0] = 8'b00010000;
risc_v_cpu.uut_instruction.memory[1] = 8'b00000011;
risc_v_cpu.uut_instruction.memory[2] = 8'b00010000;
risc_v_cpu.uut_instruction.memory[3] = 8'b00000000;
/* ADDi $0, R[0], R[7] - R[7] = 0 */ /* ADDi $0, R[0], R[7] - R[7] = 0 */
/* "000000000000_00000_000_00111_0010000" */ /* "000000000000_00000_000_00111_0010000" */
risc_v_cpu.uut_instruction.memory[4] = 32'b00000000000000000000001110010000; risc_v_cpu.uut_instruction.memory[4] = 8'b10010000;
risc_v_cpu.uut_instruction.memory[5] = 8'b00000011;
risc_v_cpu.uut_instruction.memory[6] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[7] = 8'b00000000;
/* ADDi $0, R[6], R[8] - R[8] = R[6] */ /* ADDi $0, R[6], R[8] - R[8] = R[6] */
/* "000000000000_00110_000_01000_0010000" */ /* "000000000000_00110_000_01000_0010000" */
risc_v_cpu.uut_instruction.memory[8] = 32'b00000000000000110000010000010000; risc_v_cpu.uut_instruction.memory[8] = 8'b00010000;
risc_v_cpu.uut_instruction.memory[9] = 8'b00000100;
risc_v_cpu.uut_instruction.memory[10] = 8'b00000011;
risc_v_cpu.uut_instruction.memory[11] = 8'b00000000;
/* ADD R[7], R[6], R[6] - R[6] = R[7] + R[6] */ /* ADD R[7], R[6], R[6] - R[6] = R[7] + R[6] */
/* "0000000_00111_00110_000_00110_0110000" */ /* "0000000_00111_00110_000_00110_0110000" */
risc_v_cpu.uut_instruction.memory[12] = 32'b00000000011100110000001100110000; risc_v_cpu.uut_instruction.memory[12] = 8'b00110000;
risc_v_cpu.uut_instruction.memory[13] = 8'b00000011;
risc_v_cpu.uut_instruction.memory[14] = 8'b01110011;
risc_v_cpu.uut_instruction.memory[15] = 8'b00000000;
/* ADDi $0, R[8], R[7] - R[7] = R[8] */ /* ADDi $0, R[8], R[7] - R[7] = R[8] */
/* "000000000000_01000_000_00111_0010000" */ /* "000000000000_01000_000_00111_0010000" */
risc_v_cpu.uut_instruction.memory[16] = 32'b00000000000001000000001110010000; risc_v_cpu.uut_instruction.memory[16] = 8'b10010000;
risc_v_cpu.uut_instruction.memory[17] = 8'b00000011;
risc_v_cpu.uut_instruction.memory[18] = 8'b00000100;
risc_v_cpu.uut_instruction.memory[19] = 8'b00000000;
/* JUMP - 12 */ /* JUMP - 12 */
/* 11111111111111111101_00111_1101100 */ /* 11111111111111111101_00111_1101100 */
risc_v_cpu.uut_instruction.memory[20] = 32'b11111111111111110100001011101100; risc_v_cpu.uut_instruction.memory[20] = 8'b11101100;
risc_v_cpu.uut_instruction.memory[21] = 8'b01000010;
risc_v_cpu.uut_instruction.memory[22] = 8'b11111111;
risc_v_cpu.uut_instruction.memory[23] = 8'b11111111;
`next_cycle `next_cycle
`assert_no_wait("FIBO INIT: ADDi $1, R[0], R[6] - R[6] = 1", risc_v_cpu.registers_bank.registers[6], 1) `assert_no_wait("FIBO INIT: ADDi $1, R[0], R[6] - R[6] = 1", risc_v_cpu.registers_bank.registers[6], 1)