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RISC-V_Verilog
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BOISSON Brice a815601b50
Merge pull request #2 from BriceBoisson/risc-v 
Fix: memory addressing 32 to 8 bits
 		2023-10-24 21:53:08 +09:00
rtl Fix: memory addressing 32 to 8 bits 2023-10-24 21:52:07 +09:00
scripts Add: basic element for risc-v single cycle cpu 2023-10-20 18:48:18 +09:00
sim Add: Makefile 2023-10-11 17:43:36 +09:00
tb Fix: memory addressing 32 to 8 bits 2023-10-24 21:52:07 +09:00
.gitignore Add: README 2023-10-10 16:17:16 +09:00
Makefile Add: Makefile 2023-10-11 17:43:36 +09:00
README.md Add: README 2023-10-10 16:17:16 +09:00

README.md

This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.