Add: archi and comment in top level | Fix: missing var declaration in reg test bench

2023-11-29 11:30:58 +09:00
parent 3007868c1a
commit cd6972af6d
4 changed files with 15 additions and 1 deletions
--- a/rtl/risc-v_cpu_top.v
+++ b/rtl/risc-v_cpu_top.v
--- a/rtl/risc_v_cpu_top.v
+++ b/rtl/risc_v_cpu_top.v
@@ -0,0 +1,13 @@
+module risc_v_cpu_top (input         clock, reset,
+                       output [31:0] out);
+
+    /* You can use the following file as your top layer for your FPGA synthesis */
+
+    risc_v_cpu risc_v_cpu (
+        .clock(clock),
+        .reset(reset),
+        .out(out)
+    );
+
+endmodule
+