Merge pull request #3 from BriceBoisson/test

Add: generate binary for test using gcc

Makefile

@@ -14,3 +14,6 @@ clean:
 	rm -rf transcript
 	rm -rf sim/vsim.wlf
 	rm -rf sim/simu.do
+	rm -rf tb/test_source_code/**/*.bin
+	rm -rf tb/test_source_code/**/*.elf
+	rm -rf tb/test_source_code/**/*.o

rtl/risc_v_cpu.v

@@ -69,7 +69,7 @@ module risc_v_cpu (input         clock, reset,
 
     mux2_1 #(2) mux2_pc_sel_branch (
         .in_1(pc_is_branch),
-        .in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
+        .in_2({1'b0, (alu_not ? (alu_out == 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
         .sel(pc_is_jmp),
         .out(pc_sel_in)
     );

scripts/gen_simu_do.sh

@@ -5,7 +5,8 @@ if [ $# -lt 1 ]; then
     exit 1
 fi
 
-FILE_NAME=$1
+TB_FILE_NAME=tb_$1
+FILE_NAME=$(echo "$1" | sed 's/\([[:alnum:]_]*\)[-.].*/\1/')
 
 echo 'puts "Simulation script for ModelSim"
 ' > ./sim/simu.do
@@ -15,14 +16,14 @@ if [ ! -f "rtl/""$FILE_NAME"".v" ]; then
     echo "Error: $FILE_NAME.v file not found!"
     exit 1
 fi
-if [ ! -f "tb/tb_""$FILE_NAME"".v" ]; then
+if [ ! -f "tb/""$TB_FILE_NAME"".v" ]; then
-    echo "Error: tb_$FILE_NAME.v file not found!"
+    echo "Error: ""$TB_FILE_NAME"".v file not found!"
     exit 1
 fi
 
 echo 'vlib work
 vlog ../rtl/*.v
-vlog ../tb/tb_'"$FILE_NAME"'.v
+vlog ../tb/'"$TB_FILE_NAME"'.v
 ' >> ./sim/simu.do
 
 echo 'vsim tb_'"$FILE_NAME"'

scripts/get_bin.sh

@@ -0,0 +1,23 @@
+#!/bin/bash
+
+if    [ ! command -v riscv32-unknown-elf-as &> /dev/null ] \
+   || [ ! command -v riscv32-unknown-elf-ld &> /dev/null ] \
+   || [ ! command -v riscv32-unknown-elf-objcopy &> /dev/null ]
+then
+    echo "riscv32-unknown-elf could not be found"
+    exit 1
+fi
+
+if [ $# -eq 0 ]
+then
+    echo "Usage: $0 <file>"
+    exit 1
+fi
+
+NAME=$1
+
+riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${NAME}.S -o ${NAME}.o
+riscv32-unknown-elf-ld -Ttext=0x0 ${NAME}.o -o ${NAME}.elf
+riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin
+
+# rm -rf ${NAME}.o ${NAME}.elf

sim/Makefile

@@ -1,4 +1,5 @@
 all:
+	./../scripts/get_bin.sh ../tb/test_source_code/tb_riscv_cpu/test
 	vsim -c -do "do simu.do; quit -f"
 
 debug:

tb/tb_risc_v_cpu-dyn.v

@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+`include "tb_tools.vh"
+
+module tb_risc_v_cpu ();
+    reg         clk;
+    reg         reset;
+    integer     i;
+    wire [31:0] out;
+
+    /* File management variable */
+    integer    bin_file_inputs;
+    reg [8:0]  read_instruction_1;
+    reg [8:0]  read_instruction_2;
+    reg [8:0]  read_instruction_3;
+    reg [8:0]  read_instruction_4;
+
+    risc_v_cpu risc_v_cpu (
+        .clock(clk),
+        .reset(reset),
+        .out(out)
+    );
+
+    initial begin
+        /* Reset */
+        reset = 1'b1;
+        #10
+        reset = 1'b0;
+
+        clk = 1'b0;
+
+        /* Loading Test From File */
+
+        /* Loading Binary File */
+        bin_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.bin", "r");
+        if (bin_file_inputs == 0) begin
+            $display("data_file handle was NULL");
+            $finish;
+        end
+
+        i = 0;
+        while (!$feof(bin_file_inputs))
+        begin
+            read_instruction_1 = $fgetc(bin_file_inputs);
+            read_instruction_2 = $fgetc(bin_file_inputs);
+            read_instruction_3 = $fgetc(bin_file_inputs);
+            read_instruction_4 = $fgetc(bin_file_inputs);
+            $display("read_instruction_1: %b", read_instruction_1);
+
+            if (
+                read_instruction_1[8] != 1'b1 &&
+                read_instruction_2[8] != 1'b1 &&
+                read_instruction_3[8] != 1'b1 &&
+                read_instruction_4[8] != 1'b1
+            ) begin
+                risc_v_cpu.uut_instruction.memory[i]   = read_instruction_1[7:0];
+                risc_v_cpu.uut_instruction.memory[i+1] = read_instruction_2[7:0];
+                risc_v_cpu.uut_instruction.memory[i+2] = read_instruction_3[7:0];
+                risc_v_cpu.uut_instruction.memory[i+3] = read_instruction_4[7:0];
+                i = i + 4;
+            end
+        end
+
+        for (i = 0; i < 100; i = i + 1) begin
+            `next_cycle
+            // run
+        end
+
+        // final test
+        `assert_no_wait("FOR LOOP - REG[5]: 1", risc_v_cpu.registers_bank.registers[5], 32'b1010)
+        
+        `end_message
+    end
+
+endmodule : tb_risc_v_cpu

tb/test_source_code/tb_riscv_cpu/test.S

@@ -0,0 +1,9 @@
+# t0 = 0
+li      t0, 0
+li      t2, 10
+loop_head:
+bge     t0, t2, loop_end
+# Repeated code goes here
+addi    t0, t0, 1
+j		loop_head
+loop_end: