3 Commits

Author	SHA1	Message	Date
brice.boisson	89a66cd244	Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)	2023-10-27 12:46:13 +09:00
brice.boisson	9613e2566e	Add: risc-v test bubble sort	2023-10-26 17:43:00 +09:00
brice.boisson	7c1a871e99	Add: tb registers bank	2023-10-24 20:08:36 +09:00