brice.boisson
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9613e2566e
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Add: risc-v test bubble sort
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2023-10-26 17:43:00 +09:00 |
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brice.boisson
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d51ea5c4c8
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Add: memory managing different size of opperand
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2023-10-26 16:36:32 +09:00 |
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brice.boisson
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db5d909402
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Add: begining bubble sort test | Fix: branch and imm value extension
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2023-10-25 11:07:19 +09:00 |
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brice.boisson
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ecfb4a9cc5
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Fix: change alu op_code to func
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2023-10-24 19:39:42 +09:00 |
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brice.boisson
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72d688018b
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Fix: clean name [3]
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2023-10-23 14:15:21 +09:00 |
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brice.boisson
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2c9abe91af
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Fix: clean name [2]
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2023-10-23 11:47:43 +09:00 |
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brice.boisson
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c1a099c75d
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Fix: remove useless control signal
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2023-10-23 11:37:10 +09:00 |
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brice.boisson
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dc087b24f2
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Add: set R[0] to 0
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2023-10-23 11:32:25 +09:00 |
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brice.boisson
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44ac59210c
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Fix: clean name [1]
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2023-10-23 11:24:09 +09:00 |
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brice.boisson
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54e3ecdfa3
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Fix: set right value alu auipc
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2023-10-23 09:50:51 +09:00 |
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brice.boisson
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33835ec0ed
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Fix: reset edge
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2023-10-22 22:41:39 +09:00 |
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brice.boisson
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f717284c47
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Add: assembly of risc-v cpu
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2023-10-21 22:57:58 +09:00 |