brice.boisson
|
72d688018b
|
Fix: clean name [3]
|
2023-10-23 14:15:21 +09:00 |
|
brice.boisson
|
2c9abe91af
|
Fix: clean name [2]
|
2023-10-23 11:47:43 +09:00 |
|
brice.boisson
|
c1a099c75d
|
Fix: remove useless control signal
|
2023-10-23 11:37:10 +09:00 |
|
brice.boisson
|
dc087b24f2
|
Add: set R[0] to 0
|
2023-10-23 11:32:25 +09:00 |
|
brice.boisson
|
44ac59210c
|
Fix: clean name [1]
|
2023-10-23 11:24:09 +09:00 |
|
brice.boisson
|
57216f7c85
|
Fix: use parameter to name op code
|
2023-10-23 10:10:49 +09:00 |
|
brice.boisson
|
54e3ecdfa3
|
Fix: set right value alu auipc
|
2023-10-23 09:50:51 +09:00 |
|
brice.boisson
|
766f77fa6c
|
Add: sign extension - cpu is now able to compute fibonacci
|
2023-10-23 09:41:40 +09:00 |
|
brice.boisson
|
33835ec0ed
|
Fix: reset edge
|
2023-10-22 22:41:39 +09:00 |
|
brice.boisson
|
f717284c47
|
Add: assembly of risc-v cpu
|
2023-10-21 22:57:58 +09:00 |
|
brice.boisson
|
b3fd2a827d
|
Add: basic element for risc-v single cycle cpu
|
2023-10-20 18:48:18 +09:00 |
|
brice.boisson
|
0e72c3a2e6
|
Add: Makefile
|
2023-10-11 17:43:36 +09:00 |
|
brice.boisson
|
83286df734
|
Add: Archi
|
2023-10-10 16:20:01 +09:00 |
|
brice.boisson
|
4ded2be172
|
Add: README
|
2023-10-10 16:17:16 +09:00 |
|
brice.boisson
|
4949d1f96e
|
Add: Archi
|
2023-10-10 16:13:26 +09:00 |
|