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Add: generate binary for test using gcc #3

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BriceBoisson merged 3 commits from test into main 2023-11-20 13:31:13 +00:00
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BriceBoisson commented 2023-11-20 13:31:06 +00:00 (Migrated from github.com)
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Reference: brice/RISC-V_Verilog#3
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Delete Branch "test"

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