brice/RISC-V_Verilog
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Add: generate binary for test using gcc #3

Merged
BriceBoisson merged 3 commits from test into main 2023-11-20 13:31:13 +00:00
Conversation 0 Commits 3 Files Changed 8 +116 -5

3 Commits

Author SHA1 Message Date
brice.boisson
1f9a8ceebf Add: first test 2023-11-20 22:30:19 +09:00
brice.boisson
99399cd9b3 Add: test from gcc 2023-11-20 22:20:42 +09:00
brice.boisson
93cb91f022 Add: script 2023-11-20 14:21:26 +09:00