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RISC-V_Verilog
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Divide by 4 instruction address to use space more efficiently #4

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BriceBoisson merged 2 commits from test-2 into main 2023-11-25 10:39:46 +00:00
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1 changed files with 3 additions and 1 deletions
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tb/tb_risc_v_cpu-dyn.v
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@ -92,6 +92,8 @@ module tb_risc_v_cpu ();
$finish; $finish;
end end
instruction_addr = instruction_addr / 4;
if (test[instruction_addr][5:0] == 6'b111111) begin if (test[instruction_addr][5:0] == 6'b111111) begin
test[instruction_addr][5:0] = reg_number; test[instruction_addr][5:0] = reg_number;
test[instruction_addr][37:6] = reg_test_value; test[instruction_addr][37:6] = reg_test_value;
@ -111,7 +113,7 @@ module tb_risc_v_cpu ();
for (i = 0; i < 100; i = i + 1) begin for (i = 0; i < 100; i = i + 1) begin
if (test[risc_v_cpu.program_counter.pc_addr][5:0] != 6'b111111) begin if (test[risc_v_cpu.program_counter.pc_addr][5:0] != 6'b111111) begin
curent_addr = risc_v_cpu.program_counter.pc_addr; curent_addr = risc_v_cpu.program_counter.pc_addr / 4;
`next_cycle `next_cycle
if (test[curent_addr][5:0] != 6'b111111) begin if (test[curent_addr][5:0] != 6'b111111) begin
if (test[curent_addr][5:0] < 6'b100000) begin if (test[curent_addr][5:0] < 6'b100000) begin