brice/RISC-V_Verilog
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Divide by 4 instruction address to use space more efficiently #4

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BriceBoisson merged 2 commits from test-2 into main 2023-11-25 10:39:46 +00:00
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tb/tb_risc_v_cpu-dyn.v
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@@ -112,7 +112,7 @@ module tb_risc_v_cpu ();
/* Run The Program */
for (i = 0; i < 100; i = i + 1) begin
if (test[risc_v_cpu.program_counter.pc_addr][5:0] != 6'b111111) begin
if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin
curent_addr = risc_v_cpu.program_counter.pc_addr / 4;
`next_cycle
if (test[curent_addr][5:0] != 6'b111111) begin