brice
/
RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Divide by 4 instruction address to use space more efficiently #4

Merged
BriceBoisson merged 2 commits from test-2 into main 2023-11-25 10:39:46 +00:00
Conversation 0 Commits 2 Files Changed 1 +1 -1
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit ca6d23450d - Show all commits

2
tb/tb_risc_v_cpu-dyn.v
View File

@ -112,7 +112,7 @@ module tb_risc_v_cpu ();
/* Run The Program */ /* Run The Program */
for (i = 0; i < 100; i = i + 1) begin for (i = 0; i < 100; i = i + 1) begin
if (test[risc_v_cpu.program_counter.pc_addr][5:0] != 6'b111111) begin if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin
curent_addr = risc_v_cpu.program_counter.pc_addr / 4; curent_addr = risc_v_cpu.program_counter.pc_addr / 4;
`next_cycle `next_cycle
if (test[curent_addr][5:0] != 6'b111111) begin if (test[curent_addr][5:0] != 6'b111111) begin