24 lines
825 B
Markdown
24 lines
825 B
Markdown
# RISC-V Verilog
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This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.
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This CPU will implement the RV32I ISA, with the following goals:
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- [X] Single cycle RISC-V RVI32I CPU
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- [ ] Multi cycle CPU
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- [ ] Pipelining
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- [ ] (Bonus) RISC-V privileged ISA
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# How to Run the Test
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Use the command :\
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```make TARGET=<test_bench>-<sub_test>```
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With `test_bench` among the listed test bench in the `tb` directory and `sub_test` a source code file in the `tb/test_source_code/tb_<test_bench>` directory.
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```make TARGET=risc_v_cpu-test```
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You can remove the dash and `sub_test` argument to run only the non source code based test.
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```make TARGET=risc_v_cpu```
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Or use `all` as a `sub_test` to run all test associated to a `test_bench`.
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```make TARGET=risc_v_cpu-all```
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