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BOISSON Brice 8920eb9aba
Merge pull request #4 from BriceBoisson/test-2
Divide by 4 instruction address to use space more efficiently
2023-11-25 19:39:46 +09:00
rtl Add: test from gcc 2023-11-20 22:20:42 +09:00
scripts Fix: clean environment between two test 2023-11-24 19:47:36 +09:00
sim Add: new make way enabling multiple asm generated test 2023-11-22 11:35:08 +09:00
tb Fix: divide by 4 on entry test too 2023-11-25 19:38:14 +09:00
.gitignore Add: begining bubble sort test | Fix: branch and imm value extension 2023-10-25 11:07:19 +09:00
Makefile Add: new make way enabling multiple asm generated test 2023-11-22 11:35:08 +09:00
README.md Add: change progression status 2023-10-26 17:43:49 +09:00

README.md

RISC-V Verilog

This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.

This CPU will implement the RV32I ISA, with the following goals:

  • Single cycle RISC-V RVI32I CPU
  • Multi cycle CPU
  • Pipelining
  • (Bonus) RISC-V privileged ISA