brice.boisson
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36cb472979
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Add: test PC
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2024-01-26 16:13:21 +01:00 |
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brice.boisson
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0aae6901e3
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Add: test PC
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2024-01-26 16:12:22 +01:00 |
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brice.boisson
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699b643466
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Add: tb archi for module PC
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2023-12-05 13:55:09 +09:00 |
BOISSON Brice
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e8c7cb474d
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Fix: tb reg bank delay first test after end of reset (#11)
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2023-12-05 13:54:17 +09:00 |
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brice.boisson
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d6f7fb498b
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Add: tb archi for module PC
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2023-12-05 13:51:51 +09:00 |
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BOISSON Brice
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ca6398d1e1
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Rework: separate each step of the pipeline in a different component
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2023-12-04 11:34:39 +09:00 |
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brice.boisson
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ffa137da41
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Add: binary search test source code
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2023-12-04 09:44:24 +09:00 |
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BOISSON Brice
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a0a1b26b83
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Fix: test 4 mem val to check mem value
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2023-12-04 09:43:15 +09:00 |
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brice.boisson
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ce01e2078c
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Fix: fix saved register on stack name
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2023-12-03 22:17:29 +09:00 |
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brice.boisson
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db135f06b4
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Add: syracuse test source code
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2023-11-30 14:14:53 +09:00 |
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brice.boisson
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cd6972af6d
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Add: archi and comment in top level | Fix: missing var declaration in reg test bench
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2023-11-29 11:30:58 +09:00 |
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brice.boisson
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fb95d74cd7
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Fix: 3rd test lower test value range | clean code
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2023-11-29 11:11:44 +09:00 |
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brice.boisson
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479f110cd7
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Add: power test source code
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2023-11-29 10:39:48 +09:00 |
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brice.boisson
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5e93084239
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Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench
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2023-11-28 14:24:30 +09:00 |
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brice.boisson
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91514de821
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Add: loop and multiplication source code test | expend instruction memory size | Fix: on empty test file
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2023-11-27 14:27:09 +09:00 |
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brice.boisson
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f6b6e0f285
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Fix: name of tag in branch test source code
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2023-11-27 09:55:06 +09:00 |
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brice.boisson
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8b5faa374b
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Add: neg branch test
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2023-11-27 09:47:38 +09:00 |
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brice.boisson
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9750e1ab48
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Add: branch source code test file | Fix: remove test source code test file
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2023-11-27 09:35:14 +09:00 |
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brice.boisson
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0cf217ff7b
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Add: test source code for branch instruction
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2023-11-26 22:31:27 +09:00 |
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brice.boisson
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c6ffe7e2e9
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Fix: dynamique test bench else cond
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2023-11-26 22:22:16 +09:00 |
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brice.boisson
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7949850418
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Add: new test source code + Fix: gen_bin script and bin path
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2023-11-25 23:18:24 +09:00 |
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brice.boisson
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ca6d23450d
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Fix: divide by 4 on entry test too
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2023-11-25 19:38:14 +09:00 |
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brice.boisson
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c6292d3b4f
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Add: use space more efficiently on test datastructure
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2023-11-25 19:34:07 +09:00 |
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brice.boisson
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86abae02eb
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Add: name of the dynamic test following the tested element
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2023-11-25 19:28:17 +09:00 |
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brice.boisson
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81268259ff
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Add: Formating test output
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2023-11-24 19:28:08 +09:00 |
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brice.boisson
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82474c8d16
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Fix: delete old folder
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2023-11-23 13:47:03 +09:00 |
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brice.boisson
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6f4f7f6969
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Add: new make way enabling multiple asm generated test
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2023-11-22 11:35:08 +09:00 |
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brice.boisson
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e2ca11548c
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Add: generate file on make
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2023-11-21 18:45:25 +09:00 |
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brice.boisson
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7d60960831
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Add: generate test from comment in assembly file
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2023-11-21 18:36:10 +09:00 |
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brice.boisson
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b95e79edc4
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Fix: test after imm fix
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2023-11-20 22:47:10 +09:00 |
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brice.boisson
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1f9a8ceebf
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Add: first test
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2023-11-20 22:30:19 +09:00 |
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brice.boisson
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99399cd9b3
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Add: test from gcc
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2023-11-20 22:20:42 +09:00 |
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brice.boisson
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93cb91f022
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Add: script
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2023-11-20 14:21:26 +09:00 |
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brice.boisson
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9613e2566e
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Add: risc-v test bubble sort
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2023-10-26 17:43:00 +09:00 |
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brice.boisson
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db5d909402
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Add: begining bubble sort test | Fix: branch and imm value extension
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2023-10-25 11:07:19 +09:00 |
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brice.boisson
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67c71565c0
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Fix: memory addressing 32 to 8 bits
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2023-10-24 21:52:07 +09:00 |
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brice.boisson
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0fb4170797
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Add: tb_risc_v fibonacci compute
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2023-10-24 21:19:24 +09:00 |
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brice.boisson
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7c1a871e99
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Add: tb registers bank
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2023-10-24 20:08:36 +09:00 |
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brice.boisson
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ecfb4a9cc5
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Fix: change alu op_code to func
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2023-10-24 19:39:42 +09:00 |
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brice.boisson
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6cc27cdc2f
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Add: tb alu all func
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2023-10-24 19:36:34 +09:00 |
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brice.boisson
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b99914f42d
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Add: named parameter for ALU func | alu test case
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2023-10-24 10:49:29 +09:00 |
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brice.boisson
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5829400fea
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Add: tb macro to assert
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2023-10-23 17:34:37 +09:00 |
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brice.boisson
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72d688018b
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Fix: clean name [3]
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2023-10-23 14:15:21 +09:00 |
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brice.boisson
|
33835ec0ed
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Fix: reset edge
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2023-10-22 22:41:39 +09:00 |
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brice.boisson
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f717284c47
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Add: assembly of risc-v cpu
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2023-10-21 22:57:58 +09:00 |
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brice.boisson
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b3fd2a827d
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Add: basic element for risc-v single cycle cpu
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2023-10-20 18:48:18 +09:00 |
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brice.boisson
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0e72c3a2e6
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Add: Makefile
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2023-10-11 17:43:36 +09:00 |
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brice.boisson
|
83286df734
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Add: Archi
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2023-10-10 16:20:01 +09:00 |